1. Field of Invention
This invention relates to semiconductor memories and in particular to repair using a global row redundancy.
2. Description of Related Art
Traditional redundancy schemes for repairing memory chips, such as DRAM's, has included a redundancy cell array within each block of memory cells that make up the memory chip. No separate bit line sense amplifiers are required for the redundancy cell array. Sharing of redundant rows between blocks is not allowed and parts must be scrapped if a particular block runs out of rows in a redundant cell array. This has led to a redundant scheme where a redundant cell array is provided in a separate area from the memory blocks, and each memory block contains only a memory cell array and bit line sense amplifiers. Associated with the redundant cell array are additional sense amplifiers to accommodate the repair action and as a result cause an extra area to be used for the additional sense amplifiers.
In T. Kirihata et al., "Fault-Tolerant Designs for 256 Mb Dram", Kirihata et al., IEEE Journal of Solid State Circuits, Vol. 31, No. 4, April 1996, pp 559-566, a fault tolerant design is described in which redundant word lines are provided in a 128 Kb redundancy block that is separate from the sixteen one megabit blocks of the memory array. A scheme for column redundancy is also described using interchangeable MDQ's (main data input and outputs). In U.S. Pat. No. 5,881,003 (Kirihata et al.) a method for employing a new redundancy scheme is described. The variable domain redundancy replacement scheme described creates a replacement domain out of at least two variable domains which partially overlap with respect to each other. In U.S. Pat. No. 5,831,914 (Kirihata) a variable size redundancy replacement scheme is described. A plurality of variable redundancy units are provided which makes it possible to choose the most effective redundancy unit which is most closely fitting to the size of the cluster of failures that are to be replaced. In U.S. Pat. No. 5,831,913 a row redundancy replacement scheme is described using a variable size redundancy replacement circuitry. The redundancy uses separate redundant DRAM blocks with a global redundancy. In U.S. Pat. No. 5,764,587 (Buettner et al.) a word line redundancy is described where word line decoders are selectively connected to word line drivers through switches. There are more word line drivers than word line decoders which provides the necessary redundancy.
As the number of cells in memory chips have grown, there has been a need to change the way rows of redundant cells are distributed within the memory chip. An array of redundant cells need to be accessible to all memory cells to reduce the exposure to using up redundant rows in local areas before a memory chip has been repaired. The distribution of these arrays of redundant cells need to be placed within the memory chip such that extra bit line sense amplifiers are not required, saving chip surface area.